1. Field of the Invention
The present invention relates to a reticle for a projection exposure apparatus and to an exposure method. More particularly, the present invention relates to an arrangement of alignment marks on a reticle and to an exposure method using the same.
2. Description of the Related Art
Use of a projection exposure apparatus is in a main stream manufacturing of a semiconductor device in recent years. A reticle substrate as a master for exposure is mounted on the projection exposure apparatus, and a pattern formed on the reticle substrate is transferred onto a wafer after reduction and projection. Generally, chips, alignment marks, and a process control module (PCM) for evaluating characteristics of essential elements such as a transistor and a diode are arranged on the reticle substrate.
Conventionally, the chips and the PCM are formed in different regions on the reticle substrate and the alignment marks are arranged in a chip region or a PCM region. When the alignment marks are arranged in the chip region, there arise a problem that a chip size becomes larger and the number of chips per wafer decreases. When the alignment marks are arranged in the PCM region, there arises a problem that an accuracy of the alignment is low because only one or several PCMs are formed on a wafer. In order to solve those problems, a method has been proposed in which the alignment marks are arranged in scribe lines (see Japanese Patent Application Laid-open JP 3-18012, for example).
However, in the method in which the alignment marks are arranged in scribe lines as described above newly presents a problem that metal shavings produced in dicing cannot be avoided. In order to solve the problem, a method has been proposed in which an alignment mark arrangement region is provided (see Japanese Patent Application Laid-open JP 2005-283609, for example).
However, in the method disclosed in Japanese Patent Application Laid-open JP 2005-283609, the alignment marks are arranged in a line only on one side of the reticle, and hence highly accurate alignment is difficult to attain. There is a problem that, among misalignment components including translational components, rotational components, and scaling components, components other than the translational components cannot be corrected satisfactorily, leading to a necessity for large alignment allowance, which impedes miniaturization of a semiconductor chip and decreases the number of chips per wafer.